Field programmable gate arrays (FPGAs) have evolved significantly in capacity, complexity, and speed within the last decade. Today, high-end FPGAs offer design density, speed, and IPs that can rival most high performance application-specific integrated circuit (ASIC) solutions. As a result, FPGAs have become not only a main vehicle for rapid prototyping of complex digital systems, but also have become a main component in many high-performance low-to-medium production volume systems. In the military and aerospace field in particular, there has been a steady increase of FPGA design solutions in applications that traditionally were dominated by ASICs. However, main stream FPGA designs in such mission critical systems do not implement a built-in self test (BIST) scheme that provides high fault coverage during system start-up tests. Without a high fault coverage BIST, there is a potential for system failure on the field that can result in human loss and damage to valuable resources.
Current FGPA BIST solutions exist, and they may be categorized as offline and online testing. Online testing provides the advance to testing the FPGA while it is performing system functions. Current online and offline FPGA BIST schemes generally require multiple programming files, are technology dependent, and impose an undue burden on design. For example, various offline testing schemes have been proposed to test FPGA programmable logic blocks and interconnects. A main focus of these offline schemes is to detect either faults in the configurable logic block or faults in the configurable interconnects. Generally, these schemes focus on programming part of the FPGA resources as test instrument logic—Test Pattern Generator (TPG) and Output Response Analyzer (ORA)—to test other FPGA resources. These approaches generally require multiple programming files to exhaustively test all possible faults in the FPGA logic fabrics in addition to the functional programming file. These schemes also detect faults that may not even affect the functionality of the design.
Structures using TPG and ORA are also technology dependent. Porting FPGA BIST from device families to other device families becomes a non-trivial job. Thus, although offline schemes may be well suited for FPGA device manufacture testing, they are not a good candidate for system level and field tests.
Existing online FPGA BIST schemes include concepts such as roving self-testing areas (STARs). Such online schemes generally require an intelligent controller and multiple programming files to perform dynamic partial reconfiguration of the device during normal operation. Although the STARs concept may be a good choice for fault-tolerance partial reconfiguration FPGA design, it is an overkill for FPGA start-up BIST applications.
A self-checking logic design approach for FPGA design is also known. This approach uses k-input functional cells that generate complementary outputs in fault free conditions, and a 2-rail checker cell to dynamically detect faults in the configurable logic blocks. This approach calls for a new logic synthesis algorithms specifically for this application. It also incurs up to 50% overhead which prevents it from being used as a high coverage startup BIST mechanism.
Accordingly, what is desired is the adoption of BIST in main stream FPGA design without requiring a full scan design as in ASIC BIST which is expensive for FPGA implementation. FPGA BIST should also be technology independent. In other words, FPGA BIST should be able to be mapped to different FPGA families from different vendors without changing the structure. Lastly, FPGA BIST should impose a minimum burden on the designer and at the same time provide high structural and delay fault coverage.